Red Pitaya Notes
Source Issues

Direct memory access

Introduction

Two possible approaches to sending data from the FPGA to the CPU:

The GP bus approach is fast enough for the following applications:

The HP or ACP bus approach can be used for the following applications:

There are several options for controlling the transfer of data from the ADC to the BRAM or DDR3 RAM buffers and accessing the data stored in these buffers.

Options for controlling data transfer from FPGA:

Options for controlling IP cores and HDL modules from a Linux application running on the CPU:

Options for accessing data stored in BRAM or DDR3 RAM buffers from a Linux application running on the CPU:

The applications in this repository use the following combination:

Custom IP cores

The axis_ram_writer module implements the following logic:

The axis_ram_reader module implements the following logic:

The modules have two input ports for dynamically configurable parameters:

The sts_data port outputs the current value of the address counter. It can be used to check what memory addresses the modules have already accessed.

The Verilog code of these IP cores can be found in cores/axis_ram_writer.v and cores/axis_ram_reader.v.

Custom Linux driver

The custom Linux driver is used to allocate a memory buffer using contiguous memory allocator (CMA). The ioctl function is used to allocate a memory buffer and obtain its physical address. The mmap function is used to obtain the virtual address of the memory buffer.

The source code of the custom Linux driver can be found in patches/cma.c.

Usage examples

The source code of projects using direct memory access can be found at the following links: