SDR receiver compatible with HPSDR

Introduction

This SDR receiver emulates a Hermes module with eight receivers. It may be useful for projects that require eight receivers compatible with the programs that support the HPSDR/Metis communication protocol.

The HPSDR/Metis communication protocol is described in the following documents:

This application requires the Zmod Digitizer module to be connected to the ZMOD A connector of the USB104 A7 board.

Hardware

The FPGA configuration consists of eight identical digital down-converters (DDC). Their structure is shown in the following diagram:

HPSDR receiver

The I/Q data rate is configurable and four settings are available: 48, 96, 192, 384 kSPS.

The tunable frequency range covers from 0 Hz to 61.44 MHz.

The projects/sdr_receiver_hpsdr directory contains two Tcl files: block_design.tcl, rx.tcl. The code in these files instantiates, configures and interconnects all the needed IP cores.

The projects/sdr_receiver_hpsdr/filters directory contains the source code of the R script used to calculate the coefficients of the FIR filters.

Software

The projects/sdr_receiver_hpsdr/server directory contains the source code of the UDP server (sdr-receiver-hpsdr.py) that receives control commands and transmits the I/Q data streams to the SDR programs.

This SDR receiver should work with the programs that support the HPSDR/Metis communication protocol. It was tested with the following programs:

Skimmer Server

Getting started

Running CW Skimmer Server and Reverse Beacon Network Aggregator

Building from source

The structure of the source code and of the development chain is described at this link.

Setting up the Vitis and Vivado environment:

source /opt/Xilinx/Vitis/2020.2/settings64.sh

Cloning the source code repository:

git clone https://github.com/pavel-demin/usb104-a7-notes
cd usb104-a7-notes

Building sdr_receiver_hpsdr.bit:

make NAME=sdr_receiver_hpsdr bit

Configuring the FPGA:

make NAME=sdr_receiver_hpsdr run