SDR transceiver compatible with HPSDR

Introduction

The High Performance Software Defined Radio (HPSDR) project is an open source hardware and software project that develops a modular Software Defined Radio (SDR) for use by radio amateurs and short wave listeners.

This version of the Red Pitaya SDR transceiver makes it usable with the software developed by the HPSDR project and other SDR programs that support the HPSDR/Metis communication protocol.

This SDR transceiver emulates a HPSDR transceiver similar to Hermes with a network interface, two receivers and one transmitter.

The HPSDR/Metis communication protocol is described in the following documents:

Hardware

The implementation of this SDR transceiver is similar to the previous version of the SDR transceiver that is described in more details at this link.

The main problem in emulating the HPSDR hardware with Red Pitaya is that the Red Pitaya ADC sample rate is 125 MSPS and the HPSDR ADC sample rate is 122.88 MSPS.

To address this problem, this version contains a set of FIR filters for fractional sample rate conversion.

The resulting I/Q data rate is configurable and four settings are available: 48, 96, 192, 384 kSPS.

The tunable frequency range covers from 0 Hz to 61.44 MHz.

This SDR transceiver consists of four digital down-converters (DDC) and one digital up-converter (DUC). The first two digital down-converters are connected to two ADC channels. Two additional digital down-converters are required for the amplifier linearization system. One of them is connected to the second ADC channel and the other one is connected to the output of the digital up-converter.

The basic blocks of the digital down-converters are shown on the following diagram:

DDC

The digital up-converter consists of similar blocks but arranged in an opposite order:

DUC

The projects/sdr_transceiver_hpsdr directory contains three Tcl files: block_design.tcl, rx.tcl, tx.tcl. The code in these files instantiates, configures and interconnects all the needed IP cores.

The projects/sdr_transceiver_hpsdr/filters directory contains the source code of the R scripts used to calculate the coefficients of the FIR filters.

The projects/sdr_transceiver_hpsdr/server directory contains the source code of the UDP server (sdr-transceiver-hpsdr.c) that receives control commands and transmits/receives the I/Q data streams to/from the SDR programs.

RF, GPIO and XADC connections

GPIO connections

I2S connections

The I2S interface is sharing pins with the ALEX interface. So, the two can’t be used simultaneously. The supported I2S audio codecs are TLV320AIC23B and WM8731. The I2S audio codecs should be clocked with a 12.288 MHz oscillator crystal.

The I2S interface should be connected to the extension connector E1 as shown on the above diagram. The I2C interface should be connected to the I2C pins of the extension connector E2.

ALEX connections

The ALEX module can be connected to the pins DIO4_N (Serial Data), DIO5_N (Clock), DIO6_N (RX Strobe) and DIO7_N (TX Strobe) of the extension connector E1. The board and the protocol are described in the ALEX manual.

The HPSDR signals sent to the TPIC6B595 chips are shown on the following diagram:

ALEX connections

I2C connections

This interface is designed by Peter DC2PD. The sdr-transceiver-hpsdr.c server communicates with one or two PCA9555 chips connected to the I2C pins of the extension connector E2.

HPSDR signals sent to the PCA9555 chip at address 0 (0x20):

PCA9555 pins HPSDR signals
P00 - P06 Open Collector Outputs on Penelope or Hermes
P07 - P10 Attenuator (00 = 0dB, 01 = 10dB, 10 = 20dB, 11 = 30dB)
P11 - P12 Rx Antenna (00 = none, 01 = Rx1, 10 = Rx2, 11 = XV)
P13 - P14 Tx Relay (00 = Tx1, 01= Tx2, 10 = Tx3)

HPSDR signals sent to the PCA9555 chip at address 1 (0x21):

PCA9555 pins HPSDR signals
P00 select 13MHz HPF (0 = disable, 1 = enable)
P01 select 20MHz HPF (0 = disable, 1 = enable)
P02 select 9.5MHz HPF (0 = disable, 1 = enable)
P03 select 6.5MHz HPF (0 = disable, 1 = enable)
P04 select 1.5MHz HPF (0 = disable, 1 = enable)
P05 bypass all HPFs (0 = disable, 1 = enable)
P06 6M low noise amplifier (0 = disable, 1 = enable)
P07 disable T/R relay (0 = enable, 1 = disable)
P10 select 30/20m LPF (0 = disable, 1 = enable)
P11 select 60/40m LPF (0 = disable, 1 = enable)
P12 select 80m LPF (0 = disable, 1 = enable)
P13 select 160m LPF (0 = disable, 1 = enable)
P14 select 6m LPF (0 = disable, 1 = enable)
P15 select 12/10m LPF (0 = disable, 1 = enable)
P16 select 17/15m LPF (0 = disable, 1 = enable)

More information about the I2C interface can be found at this link.

Software

This SDR transceiver should work with most of the programs that support the HPSDR/Metis communication protocol:

Getting started

Amplifier linearization

PowerSDR mRX PS includes an amplifier linearization system called PureSignal. The following screenshots show what settings should be adjusted when using it with Red Pitaya. To access the “Calibration Information” panel press Ctrl+Alt+i. The attenuated feedback signal from the amplifier should be connected to IN2.

PowerSDR Hardware Config

PowerSDR Linearity

The following spectra illustrate how the amplifier linearization works with the Red Pitaya output (OUT1) connected to the Red Pitaya input (IN2) with a 50 Ohm termination.

PureSignal off PureSignal on

CW functionality

The CW keyer can be used with a straight or iambic key connected to the pins DIO1_N and DIO2_N of the extension connector E1. The CW signal is generated when one of the CW modes is selected in PowerSDR mRX PS and the pins DIO1_N and DIO2_N are connected to GND.

The ramp generator is programmable. The default ramp’s shape is the step response of the 4-term Blackman-Harris window. It’s inspired by the “CW Shaping in DSP Software” article appeared in the May/June, 2006 issue of QEX.

The measured delay between the key press and the start of the RF signal is about 2 ms. The 10%-90% rise time of the signal is about 3.5 ms.

CW signal

The following figure shows the spectrum of the CW signal keyed at 50 WPM.

CW spectrum

Building from source

The installation of the development machine is described at this link.

The structure of the source code and of the development chain is described at this link.

Setting up the Vivado environment:

source /opt/Xilinx/Vivado/2016.4/settings64.sh

Cloning the source code repository:

git clone https://github.com/pavel-demin/red-pitaya-notes
cd red-pitaya-notes

Building sdr_transceiver_hpsdr.bit:

make NAME=sdr_transceiver_hpsdr bit

Building sdr-transceiver-hpsdr:

arm-linux-gnueabihf-gcc -static -O3 -march=armv7-a -mcpu=cortex-a9 -mtune=cortex-a9 -mfpu=neon -mfloat-abi=hard -D_GNU_SOURCE projects/sdr_transceiver_hpsdr/server/sdr-transceiver-hpsdr.c -o sdr-transceiver-hpsdr -lm -lpthread

Building SD card image zip file:

source helpers/build-all.sh