SDR receiver compatible with HPSDR


This version of the SDR receiver emulates two Hermes modules with eight receivers. It may be useful for projects that require sixteen receivers compatible with the programs that support the HPSDR/Metis communication protocol.

The HPSDR/Metis communication protocol is described in the following documents:


The FPGA configuration consists of sixteen identical digital down-converters (DDC). Their structure is shown on the following diagram:

HPSDR receiver

The I/Q data rate is configurable and four settings are available: 48, 96, 192, 384 kSPS.

The tunable frequency range covers from 0 Hz to 61.44 MHz.

The projects/sdr_receiver_hpsdr_122_88 directory contains two Tcl files: block_design.tcl, rx.tcl. The code in these files instantiates, configures and interconnects all the needed IP cores.

The projects/sdr_receiver_hpsdr_122_88/filters directory contains the source code of the R scripts used to calculate the coefficients of the FIR filters.

The projects/sdr_receiver_hpsdr_122_88/server directory contains the source code of the UDP server (sdr-receiver-hpsdr.c) that receives control commands and transmits the I/Q data streams to the SDR programs.


This SDR receiver should work with most of the programs that support the HPSDR/Metis communication protocol:

Getting started

Running CW Skimmer Server and Reverse Beacon Network Aggregator

Building from source

The installation of the development machine is described at this link.

The structure of the source code and of the development chain is described at this link.

Setting up the Vitis and Vivado environment:

source /opt/Xilinx/Vitis/2020.2/

Cloning the source code repository:

git clone
cd red-pitaya-notes

Building sdr_receiver_hpsdr_122_88.bit:

make NAME=sdr_receiver_hpsdr_122_88 PART=xc7z020clg400-1 bit

Building SD card image zip file:

source helpers/