SDR receiver

Some interesting links on digital signal processing and software defined radio:

Short description

The implementation of the SDR receiver is quite straightforward:

The tunable frequency range covers from 0 Hz to 50 MHz.

The I/Q data rate is configurable and four settings are available: 50, 100, 250 and 500 kSPS.

Digital down-converter

The basic blocks of the digital down-converter (DDC) are shown on the following diagram:

SDR receiver

The in-phase/quadrature (I/Q) demodulator is implemented using the CORDIC algorithm. CIC filter is used to decrease the data rate by a configurable factor within the range from 125 to 1250. FIR filter compensates for the drop in the CIC frequency response, filters out high frequencies and reduces the data rate by a factor of two.

FIR filter coefficients are calculated with the following code in R:


# CIC filter parameters
R <- 125                       # Decimation factor
M <- 1                         # Differential delay
N <- 6                         # Number of stages

Fo <- 0.22                     # Pass band edge; 220 kHz

# fir2 parameters
k <- kaiserord(c(Fo, Fo+0.02), c(1, 0), 1/(2^16), 1)
L <- k$n                       # Filter order
Beta <- k$beta                 # Kaiser window parameter

# FIR filter design using fir2
s <- 0.001                     # Step size
fp <- seq(0.0, Fo, by=s)       # Pass band frequency samples
fs <- seq(Fo+0.02, 0.5, by=s)  # Stop band frequency samples
f <- c(fp, fs)*2               # Normalized frequency samples; 0<=f<=1

Mp <- matrix(1, 1, length(fp)) # Pass band response; Mp[1]=1
Mp[-1] <- abs(M*R*sin(pi*fp[-1]/R)/sin(pi*M*fp[-1]))^N
Mf <- c(Mp, matrix(0, 1, length(fs)))

h <- fir2(L, f, Mf, window=kaiser(L+1, Beta))

# Print filter coefficients
paste(as.character(h), collapse=", ")

To get an idea of the combined (CIC and FIR) filter response, the following figure shows a 256k FFT display from the SDR# program when Red Pitaya inputs are not connected to anything:

Filter response

The projects/sdr_receiver directory contains one Tcl file block_design.tcl that instantiates, configures and interconnects all the needed IP cores.

The projects/sdr_receiver/server directory contains the source code of the TCP server (sdr-receiver.c) that transmits the I/Q data stream (up to 2 x 32 bit x 500 kSPS = 30.5 Mbit/s) to the SDR programs and receives commands to configure the decimation rate and the frequency of the sine and cosine waves used for the I/Q demodulation.

User interface

The I/Q data coming from Red Pitaya can be analyzed and processed by a SDR program such as SDR# or HDSDR.

The SDR programs are communicating with the SDR radio hardware through an External Input Output Dynamic Link Library (ExtIO-DLL). The detailed specifications of this interface and the source code examples can be found at the following links:

Based on the example ExtIO DLL, I’ve developed a simple ExtIO plug-in for the Red Pitaya SDR receiver. The projects/sdr_receiver/ExtIO_RedPitaya directory contains the source code of this plug-in.

The ExtIO plug-in can be built from the source code with Microsoft Visual C++ 2008 Express Edition.

A pre-built ExtIO plug-in for the Red Pitaya SDR receiver can be downloaded from this link.

For both SDR# and HDSDR, the ExtIO_RedPitaya.dll file should be copied to the directory where the program is installed and the program will recognize it automatically at start-up.


Inspired by the “Wideband active loop antenna” article appeared in the January, 2000 issue of Elektor Electronics, I’ve built my antenna using 4 wire telephone cable (9 m, 4 x 0.2 mm2). A schematic and picture of the antenna connected to Red Pitaya is shown in the following figure:

Antenna schematic Antenna picture

With this antenna I can receive some MW and SW broadcast stations.

Screen shot and audio sample

Signal from a 300 kW broadcast MW transmitter, 25 km from the transmitter:

Strong signal

Audio sample

Getting started

Building from source

The installation of the development machine is described at this link.

The structure of the source code and of the development chain is described at this link.

Setting up the Vitis and Vivado environment:

source /opt/Xilinx/Vitis/2020.2/

Cloning the source code repository:

git clone
cd red-pitaya-notes

Building sdr_receiver.bit:

make NAME=sdr_receiver bit

Building SD card image zip file:

source helpers/